In general, the present invention relates to a technology for defining specifications of interface portions of plural circuit modules and making connection between the circuit modules easy by using the specifications in an integrated-circuit system or a digital system having the circuit modules connected to each other. More particularly, the present invention relates to a storage medium for recording the specifications and a method of presenting information defining the specifications.
With the increased scale of LSI integration, it becomes possible to include most elements required in the configuration of a system in a single semiconductor chip. When designing an LSI having elements of a large-scale system, it is possible to reduce the design cost and the number of design works by utilizing already designed circuit modules owned as assets or circuit modules purchased from vendors in the design. One of biggest challenges encountered in such a design technique is how to make the already designed circuit modules reusable. One of solutions to the problem of the challenge is described in a reference authored by Kei Suzuki, the inventor of the present invention. The reference having a title of xe2x80x9cOwL: An Interface Description Language for IP Reusexe2x80x9d was presented to a Custom Integrated Circuit Conference in the year of 1999. On pages 403 to 406, there are described values of signals appearing at input/output ports of each function of every circuit module at particular times. By expressing an operation of a circuit module in terms of specifications or functions and timing charts of the circuit module in a computer by using a state transition machine, it is thereby possible to use the computer as a tool for aiding the designer understand the specifications of the circuit module. In addition, the reference also describes automation of design works such as verification for feasibility to connect 2 given circuit modules and a synthesis of signal patterns.
With the method of expressing module specifications based on the proposed conventional state machine, however, a combination of signal values observed at particular times during the operation of a circuit module is expressed as 1 transition of the state machine For this reason, first of all, it is necessary to define a combination of possible signal values as a transition. Assume for example that a combination of values of signals controlling an operation mode of a circuit is defined. Even if the value of only one of the signals changes, a new combination of the signals with the values of the remaining signals unchanged needs to be defined. This definition entails a large number of man-months required for a module with a large number of ports. A problem similar to the one described above rises in the case of a module having plural interfaces or a module having plural sub-modules. That is, when expressing all interfaces of a module, it is necessary to define all combinations of all possible values of all signals generated by the module as a whole. Thus, a person receiving specifications of modules must define combinations from the interfaces by considering possible signal states for each unit time, entailing a large number of man-months needed during the work to synthesize the interfaces. In addition, there is also a shortcoming that, after the interfaces are synthesized, functions developed at each of the interfaces are difficult to recognize. On the other hand, specifications can be defined for each interface In this case, however, there is raised a problem of impossibility to grasp an interface in a module as a whole.
Moreover, in the method of expressing module specifications based on the proposed conventional state machine, a combination of signal values at a certain particular time must be defined. Thus, there was adopted a protocol difficult to express. Determination of parity of a data signal in a parity signal of a PCI bus always lagging by 1 cycle is an example of this protocol. In order to express this protocol by adopting the conventional method, it is necessary to store the value of a data signal in a variable for each cycle and to carry out processing by referencing the variable. Furthermore, a sequence of operations to store the value of a data signal in a variable and to reference the variable must be controlled correctly.
In addition, in the conventional method to express specifications of a circuit module, the only information following signal variations is an identifier name. In the present state of the art, the meanings of a signal variation and a function related to the signal variation are not known to the user. For example, it is impossible to determine whether the user is capable of directly using a function of a circuit module or the function is merely a portion of a certain function and cannot thus be used directly by the user. Moreover, in the method of expressing module specifications based on the proposed conventional state machine, a sequence of signal variations from the start of the operation of a circuit module is defined so that it is difficult to express a discontinued operation In the event of an error occurring during an operation of an actual circuit or at an intentional hardware/software reset, the operation may be restarted from an initial state. In order to express this operation by using the conventional method, all functions are required to be terminatable at any time.
An object of the present invention addressing the problems described above is to provide a storage medium for recording definitions of interface specifications, information transmission media and an information presentation method, which require no large number of man-months despite a large number of circuit-module ports.
Another object of the present invention is to provide a storage medium for recording definitions of interface specifications, information transmission media and an information presentation method, which allow all interfaces of a circuit module to be identified with ease.
In order to achieve the objects described above, in accordance with a representative aspect of the present invention discovered by the inventor, there are provided a method for presenting interface information of a circuit module, a computer-readable storage medium used for storing the interface information and media for disseminating the interface information The interface information has high-level combinations each including first identifier sets and second identifier sets where:
the first identifier sets are each a combination pattern of values of signals each appearing at a predetermined time at one of ports pertaining to a first port set of the circuit module; and
the second identifier sets are each a combination pattern of values of signals each appearing at a predetermined time at one of ports pertaining to a second port set of the circuit module.
Information prescribed in each of the high-level combinations each including the first identifier sets associated with the port set and the second identifier sets associated with the second port set defines an intergroup-level function of the circuit module.
In accordance with another aspect of the present invention, there are provided a method for presenting interface information of a circuit module, a computer-readable storage medium used for storing the interface information and media for disseminating the interface information. The interface information stored in the storage medium has high-level combinations each including first identifier sets and second identifier sets where:
the first identifier sets are each a combination pattern of values of signals each appearing at a predetermined time at one of ports pertaining to a first port set of the circuit module; and
the second identifier sets are each a combination pattern of values of signals each appearing at a predetermined time at one of ports pertaining to a second port set of the circuit module.
Interface information of the first port set and interface information of the second port set define a function of the module circuit where the interface information of the first port set is a chronological sequence of the high-level combinations each including the first identifier sets associated with the port set whereas the interface information of the second port set is a chronological sequence of the high-level combinations each including the second identifier sets associated with the second port set.
In accordance with a still other aspect of the present invention, there is provided a circuit module""s interface information having a chronological sequence of identifiers each representing a combination pattern of values of signals each appearing at a first predetermined time at one of ports pertaining to a first port set of the circuit module and a combination pattern of values of signals each appearing at a second predetermined time different from the first predetermined time at one of ports pertaining to a second port set of the circuit module.
In accordance with a further aspect of the present invention, there is provided a storage medium for recording:
a set of identifiers each representing a combination pattern of values of signals each appearing at a predetermined time at one of ports pertaining to any port set of the circuit module; and
a set of definitions each defining a function of the circuit module as a chronological sequence of the identifiers included in the set of identifiers,
wherein the definitions each include:
information indicating whether or not resetting of the function is possible; and
information indicating a parallel or serial format.
In accordance with a still further aspect of the present invention, there is provided a connection-verifying method for determining whether or not a first circuit module can be connected to a second circuit module, the connection-verifying method having the processing steps of:
verifying existence of a relation between a function of the first circuit module and a function of the second circuit module; and
finding arrival steps of the function of the first circuit module and the function of the second circuit module by using a chronological array of identifiers each representing the function of the first circuit module and a chronological array of identifiers representing the function of the second circuit module; and
determining whether or not the first circuit module can be connected to the second circuit module in dependence on whether or not the arrival step of the function of the first circuit module overlaps the arrival step of the function of the second circuit module,
wherein:
the processing steps are based on interface information of the first circuit module and interface information of the second circuit module;
the interface information of the first circuit module has high-level combinations each including first identifier sets and second identifier sets where:
the first identifier sets are each a combination pattern of values of signals each appearing at a predetermined time at one of ports pertaining to a first port set of the first circuit module, whereas
the second identifier sets are each a combination pattern of values of signals each appearing at a predetermined time at one of ports pertaining to a second port set of the second circuit module; and
the interface information of the second circuit module has high-level combinations each including third identifier sets and fourth identifier sets where:
the third identifier sets are each a combination pattern of values of signals each appearing at a predetermined time at one of ports pertaining to a third port set of the second circuit module, whereas
the fourth identifier sets are each a combination pattern of values of signals each appearing at a predetermined time at one of ports pertaining to a fourth port set of the second circuit module
It should be noted that the above and other objects of the present invention as well as novel features of the invention for achieving the objects will become apparent from a study of this specification with reference to accompanying diagrams.